FIELD OF THE INVENTION
This invention relates in general to the fabrication of metal oxide semiconductor field effect transistor (MOSFET), and more particularly to the fabricating of a lightly doped drain (LDD) structure. A gate with a particular configuration is formed by a photoresist layer with a particular configuration. Then, a step of ion implantation is performed, using the gate with a particular configuration as a mask, to form a lightly doped drain structure of a MOSFET.
One of the most important tendency of modern integrated circuit (IC) fabricating technique is to develop smaller line width devices. As the channel length is reduced but the voltage provided remains as usual, the lateral electric field of the channel increases. Therefore, the energy of the electrons in the channel obtained from electric field speeding increases, especially in the area around the junction of the channel and the source/drain region. These electrons have higher energy than other electrons in thermal equilibrium so that they are called hot electrons. Some of the hot electrons even arrive in the gate oxide layer. The resulting electric holes immigrate to the semiconductor substrate and therefore results in leakage current.
To reduce the hot electron effect as fabricating a short channel MOS, the design of an LDD structure is used to prevent leakage current. The LDD structure includes a more lightly doped region near the channel.
To further understand the LDD structure of a MOS field effect transistor, an NMOS on a p-substrate is taken as an example.
Referring to FIG. 1A, on a p-substrate 1, a field region 2 is formed to isolate the adjacent MOS device. The field region 2 can be formed by local oxidation of silicon (LOCOS) or shallow trench isolation (STI). STI technique is performed by first forming trenches in the p-substrate 1 and then filling oxide into the trenches, using chemical vapor deposition, to form field oxide region 2. An oxide layer 4 is then formed by thermal oxidation. A polysilicon layer 6 is formed on the oxide layer. The polysilicon layer 6 is typically formed by depositing polysilicon, using low pressure chemical vapor deposition (LPCVD), doping and finally annealing to activate the dopant so that the conductivity of the polysilicon layer is increased. Then, a photoresist layer 8 is formed on the polysilicon layer 6.
Next, referring to FIG. 1B, the photoresist layer 8 is patterned to form a photoresist layer 8a. Using the patterned photoresist layer 8a as a mask, the oxide layer 4 and the polysilicon layer 6 are anisotropically etched to define the gate oxide layer 4a and the gate polysilicon layer 6a.
Referring to FIG. 1C, the patterned photoresist layer 8a is removed.
Then, PMOSs on the substrate 1 are covered by a mask (not shown). Referring to FIG. 1D, ion implantation process is performed to form a lightly doped source/drain region 10 with 1.times.10.sup.13 /cm.sup.2 .about.1.times.10.sup.14 /cm.sup.2 of P.sup.31 using an energy level of about 30 KeV.about.100 keV. The doping depth is about 0.02 .mu.m.about.0.15 .mu.m.
Referring to FIG. 1E, an oxide layer is deposited over the whole surface of the device structure by chemical vapor deposition. An anisotropic etching back is performed to etch back the oxide layer to form a spacer 12 around the gate polysilicon layer 6a and gate oxide layer 4a.
Referring to FIG. 1F dopant of high concentration is than implanted into the substrate. After annealing, source/drain regions with LDD structure, having a first concentration region 10a and a second concentration region 10b are formed. The dopant concentration of the first concentration region 10a is lower than the one of the second concentration region 10b. The high concentration dopant can be P.sup.31, the energy can be about 150 KeV.about.500 KeV, the dosage of the ion implanted can be 1.times.10.sup.13 /cm.sup.2 .about.1.times.10.sup.14 /cm.sup.2 and the depth can be about 0.2 .mu.m.about.0.6 .mu.m.
Conventionally, two masks and two steps of ion implantation for lightly doped drain structure are required for a substrate having both NMOS FETs and PMOS FETs. Also, after the formation of the spacers, further two masks and two ion implantation steps for forming source/drain regions are needed for forming the whole LDD structure.